There is an ever-increasing desire for faster and more compact semiconductor memory with an increasing amount of functionality. One challenge in the design of memory subsystems involves utilizing readily available manufacturing techniques and materials. In many cases, a memory subsystem designer may have limited control of some of the components of the system, or as is sometimes the case in memory subsystems, many components of the memory subsystem are defined by actual or de-facto standards. Extreme economic demands are placed on the memory subsystem designer to find techniques to improve the speed and capacity of the subsystem while maintaining high reliability standards, low cost, and small form factor.
Commercial embodiments of memory systems often contain a memory controller, package and PCB interconnects, and at least one dual in-line memory module (DIMM). Often, the topology of the electrical connectivity between a memory controller and one or more DIMMs is characterized by different interconnect distances between the memory controller and DIMM #1, DIMM #2, DIMM#3, etc. Such a configuration is known as a multi-drop bus topology.
A structure of transmission conductor, dielectric substrate material, and conductive reference plane is often referred to as a transmission line, for carrying signals. A group of transmission lines connecting multiple chips are usually called a channel. The transmission channel has higher transmission bandwidth if its impedance profile is better matched along the channel. As DIMMs are added to the multi-drop configuration, additional capacitive loads as well as additional impedance discontinuity points are presented in the transmission channel, which in turn may have the effect to decrease the maximum speed of communication through the channel.
Capacitive loading limits the maximum channel bandwidth. Additionally, impedance discontinuity of the channel exhibits the inherently undesirable phenomenon of multiple reflections and resonance, both of which phenomenon tend to decrease the maximum speed of communication through the channel. There is thus a need for addressing these and/or other issues associated with the prior art.